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The resistance-capacitance (RC) delay due to interconnect metal layers needs to be reduced as the semiconductor industry drives toward faster circuits. Due to its low resistivity and high electromigration resistance, copper has. been applied in sub-micron and deep sub-micron integrated circuits as an interconnection substitute for aluminum [6.1]. However, the problem for copper is that it is hard...
The with-in wafer non-uniformity (WIWNU) of the material removal rate (MRR) has long been a concern in CMP. For instance, the rapid variation of the material removal rate at the wafer edge, also known as edge effect, requires an exclusion of the wafer edge after CMP. This reduces the yield of the process. In the shallow trench isolation and copper damascene process, the uneven material removal rates...
In Chapter 6, a one and semi-two dimensional model based on linear elasticity and viscoelasticity is developed to investigate feature- and die-scale topography evolution. The influences of lateral directional parameters such as line width on the topography evolution in the vertical direction can be evaluated using the look-up table based semi-two dimensional model. The advantage of the model is that...
Although chemical mechanical planarization (CMP) is widely applied in integrated circuit fabrication, it is still a process of trial and error. Understanding the basic mechanism of this process has initiated research efforts from both industry and academia in the last decade. This chapter reviews previous CMP modeling efforts.
The material removal rate in the solid-solid contact mode of CMP usually increases linearly with the abrasive weight concentration. This is observed experimentally [5.3–5.6] [5.38]. However, this linear increase only holds for a limited range of abrasive weight concentrations. Two exceptions exist. First, when there are no or few abrasives in the slurry, the material removal is usually close to zero...
The last fifteen years have seen the broad application of chemical-mechanical planarization, also known as chemical-mechanical polishing (CMP), in sub-micron integrated circuit (IC) fabrication. During a CMP process, a silicon wafer with size (diameter) ranging from 4 inch (100mm) to 12 inch (300mm), patterned or blanket, is rotated about its axis while being pressed facedown by a carrier against...
The CMP process has been widely accepted in the semiconductor industry for oxide dielectric and metal layer planarization [3.1]. It is used to insure that the interconnects between multi-layer chips are achieved reliably and that the thickness of dielectric materials is uniform and sufficient. During CMP processes, a wafer is rotated about its axis while being pressed facedown by a carrier and a carrier...
The understanding of the material removal mechanism in CMP should be based on understanding the roles of the cutting tools, namely, the abrasives, and their interactions with other important input values such as the pad, chemical and wafer materials. The effect of abrasive size distribution in chemical-mechanical planarization has long been observed [4.1–4.7] [4.13] [4.14]. For example, experimental...
Summary Chemical mechanical planarization models at three scales, namely, particle scale, feature and die scales and wafer scale, are presented in this work.
This book is the product of a developing research focus on CMP at Berkeley. Its focus is on the important area of process models which have not kept pace with the tremendous expansion of applications of CMP. It specifically deals with the development of models with sufficient detail to allow the evaluation and tradeoff of process inputs and parameters to assess impact on quality or quantity of production...
It is important for logistics-planners to comprehensively measure the scale of logistics, but the scale is difficult to predict. A prediction method of turnover volume based on grey theory is studied. According to the deficiency of ordinary GM(1,1) model, an information renewal GM(1,1) predicting model of turnover volume is established. Moreover the model is applied to predict the turnover volume...
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics...
Thickness range, i.e. the difference between the highest point and the lowest point of the chip surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm that seeks to minimize the thickness range of the chip surface during the copper damascene process. The proposed solution considers the physical mechanisms in the damascene process, namely ECP (which is the process...
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