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In a 32btimes32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due...
This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement...
A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction...
A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. Ion of 525/295 muA/mum at Ion of 20 muA/mum and Ion of 780/400 muA/mum at Ioff of 3 nA/mum with supply voltage...
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