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InP Bi-CMOS technology capable of wafer-scale device-level heterogeneous integration (HI) of InP HBTs and CMOS has been developed. With this technology, full simultaneous utilization of III-V device speed and CMOS circuit complexity is possible. Simple ICs and test structures have been fabricated, showing no significant CMOS or HBT degradation and high heterogeneous interconnect yield. The heterogeneously...
Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain-bandwidth product of 40-130 GHz and low frequency gain > 45 dB . The use of InP DHBTs supports a > 6.9 V differential output swing and a slew rate > 4 times...
The performance advantages of InP based devices over silicon devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. A large...
Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain- bandwidth product of 40-130 GHz and low frequency gain >45 dB. The use of InP DHBTs supports a 6.9 V differential output swing and a slew rate >4times104 V/mus...
We have developed a process for the re-growth of InP-DHBTs on selectively implanted subcollectors for the purpose of reducing the base-collector capacitance. Si+ sub-collector implants were performed at >200degC to minimize damage, an important criterion for achieving smooth morphologies in the re-grown devices. Spectroscopic ellipsometry was used to gauge the amount of implant-induced damage in...
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