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This paper describes a low-voltage design for a pipelined A/D converter that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output range of all MDACs by 50% compared with the ADCpsilas input. We designed a 10-b pipelined ADC with the...
Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper presents a case study of a different direction, a chip multiprocessor (CMP) with a smaller processor core than a baseline high-end 130-nm 64-bit SPARC server uniprocessor. We demonstrate that the size of the baseline processor core can be reduced by...
A 3D integration custom stack system utilizing a local wireless interconnect (LWI) and a global wireless interconnect (GWI) is proposed. The LWI transfers Gb/s pulses using resonant coupling of spiral inductors with low-power dissipation of several mW. The GWI transfers global clocks and data on a 20 GHz signal using on-chip antennas.
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