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A low-cost method for nanostencil fabrication is demonstrated. The micro-stencils were fabricated by means of standard MEMS processes of conventional photolithography and bulk etching of Si substrate. The size of the micro-apertures was reduced down to sub-micron-meter scale by the additional deposition of SiO2 on SiN stencil membrane. In this study, 500- mum-thick SiO2 were deposited by PECVD from...
Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced X-ray emission spectrometry (LEXES) and other...
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