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A novel PN diode decoding method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming...
An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device,...
This paper presents a new method to improve the resolution of integral imaging. According to integral imaging system principle, a volume pixel of 3D scene is projected in several elemental images through micro-lens array. Contrary optic-ray pickup method is introduced in the CIIR process to reconstruct integral image by acquiring multiple pixels from various elemental images for corresponding volume...
Integral imaging (II) is a three-dimensional (3D) imaging technique that can record and display a 3D scene using a lenslet array or a pinhole array. In this paper, we research on low-resolution of computational reconstructed 3D images and propose a method of improving visual quality of computational II reconstructed images. The proposed method extracts pixels block from each elemental image, and then...
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