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FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (Vth), off-state current (IOFF)> drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides...
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