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Present trend towards multiprocessor and multi-core architectures as well as programmable NICs (Network Interface Cards) provides new opportunities to exploit the available parallelism in the network interface design and implementation to cope with the high communication overhead required to take advantage of a multi-gigabit links. In this paper we have used dynamic web servers to evaluate several...
In this paper, we propose a network interface that takes advantage of the parallelism available in network processors to improve the communication performance. Morespecifically, our proposal is based on the Intel IXP28xx network processor, as it includes sixteen processing cores with multithreading and an optimized design for packet processing. Thus, the proposed interface facilitates the exploitation...
The availability of multi-core processors and programmable NICs (Network Interface Cards), such as TOEs (TCP/IP Offloading Engines), provides new opportunities for designing efficient network interfaces to cope with the gap between the improvement rates of link bandwidths and microprocessor performance. This gap poses important challenges related with the high computational requirements associated...
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