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An experimental investigation reports on the effectiveness of multi-path and metal-stacking structure in regard to quality factor improvement for on-chip 8-shaped inductors on standard CMOS process. It is found that the multi-path structure has little positive impact on the 8-shaped inductors, while the metal-stacking structure improves quality factor significantly. For a 0.5 nH 8-shaped inductor...
N-channel, lateral, double-diffused MOS (NLDMOS) devices with finger-type, square-type, and octagon-type layout styles are investigated and fabricated in a 0.5-μm 18 V CMOS-DMOS (CDMOS) process. The square-type nLDMOS achieves the highest ESD failure current of 4.7 A and is also the device occupying the smallest chip area among the three layout styles. In view of the area efficiency, the square-type...
A 2.9 GHz quadrature VCO designed in a 0.18 um CMOS process achieves a very wide tuning range of 77% when the supply voltage equals 1.8 V. The phase noise is -120 dB/Hz at 1MHz offset for the oscillation frequency of 2 GHz, and -104 dB/Hz at 1MHz offset for the oscillation frequency of 4 GHz. The coupled oscillator architecture is adopted to widen tuning range and to minimum phase noise. Accurate...
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