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Resistive switching memory (RRAM) devices are gaining momentum as next generation memory technology for high density and embedded storage. To support technology development by the industry, the scaling and reliability of 1 kb RRAM must be understood and predicted. This work addresses data retention of resistance states in RRAM arrays based on HfO2. We develop a new method for studying retention statistics...
A low phase noise, small power dissipation and small sized K-band cascode differential voltage-controlled oscillator (VCO) with capacitive feedback topology using 0.18 μm CMOS technology is described. The VCO operated can be tuned between 19.1 GHz and 20.9 GHz and has low phase noise of -108.67 dBc/Hz at a 1 MHz offset. The output power of the 20.7 GHz is about -21.12 dBm. The Figure of merit (FOM)...
A low-power and high-performance RFCMOS SoC GPS receiver is introduced in this paper. It is fabricated in a 0.11 mum process with 6.2times6.2mmz TFBGA package. The power consumption is 34 mW during tracking stage and 45 mW during acquisition stage. The tracking sensitivity is up to -165 dBm with the most competitive TTFF performance. This GPS receiver is designed for PND/GSM/CDMA handsets and is compatible...
Tins paper presents the comparison of signal quality and efficiency performance between simulation and experiment for a linear RF transmitter based on a hybrid quadrature polar modulation (HQPM) architecture with digital predistortion scheme. Adjacent channel power ratio (ACPR) with and without applying the baseband predistorter are both shown to demonstrate improvement in transmitter linearity. The...
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