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This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with effective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively...
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