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This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 μm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes...
This paper presents a 1.2V CMOS RSSI based on successive detection structure. An equation estimating the maximum nonlinear error is derived and the simulation results show it is more accurate than the former one proposed by P. C. Huang. The RSSI achieves a wide bandwidth from 1MHz to 500MHz. The linear dynamic range is at least 80dB. The nonlinear error based on single frequency curve fitting is within...
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