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Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we...
Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated...
The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures.
This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most influence...
This paper presents two new conflict-driven techniques for improving transition fault coverage using multiple scan chains. These techniques are based on a novel test application scheme, in order to break the functional dependency of broadside testing. The two new techniques analyze the ATPG conflicts in broadside test generation, and try to control the flip-flops with most influence on the fault coverage...
Many X-Filling strategies are proposed to reduce test power during scan based testing. Because their main motivation is to reduce the switching activities of test patterns in the test process, some of them are prone to reduce the test ability of test patterns, which may lead to low defect coverage. In this paper, we propose a segment based X-filling(SBF) technique to reduce test power using multiple...
Two conflict-driven schemes and a new scan architecture based on them are presented to improve fault coverage of transition fault. They make full use of the advantages of broadside, skewed-load and enhanced scan testing, and eliminate the disadvantages of them, such as low coverage, fast global scan enable signal and hardware overhead. Test power is also a challenge for delay testing, so our method...
The small delay defects testing has two challenges. One is that the longest testable path selection for every target fault in ATPG consumes much CPU time. The other is the test data volume are very large. In this paper, we propose two strategies to resolve these two problems. A new path selection in advance scheme is proposed to accelerate ATPG. It aims to find fewer paths and cover more faults in...
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