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A flexible, digital-dominant wireless receiver in implemented in 65nm CMOS. The receive chain consists of a wide-band LNA, mixers, and baseband amplifiers. A 7b 21MS/s SAR ADC with embedded, configurable DT FIR/IIR filtering rejects aliasing interferers. Interleaving of sampling and SAR in the ADC maximizes conversion rate. The receiver achieves -92 dBm sensitivity, +33dB and +39dB adjacent and alternate...
A reconfigurable FIR filter and 9b SAR ADC combination in 0.13 mum CMOS is presented. The filter does not require additional analog circuitry, but is implemented by using the SAR capacitor array with a modified tracking and sampling scheme. The prototype filter-ADC can be digitally configured as a 4-tap filter, as one of two different 12-tap filters, or without any filtering. The prototype occupies...
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