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In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.
This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements...
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