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A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 ?? 103 gates with area and performance...
A new systolic array based architecture is introduced for variable block-size motion estimation (VBSME). This comprises a 2D array structure for SAD value computation combined with a parallel adder tree and a SAD comparator unit. Parallel raster scan is applied leading to high processor utilization. The exhibits much simpler control and lower hardware cost compared with previous circuits and can handle...
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