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In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET...
In present work, the impact of channel material engineering and gate oxide engineering on the RingFET architecture has been investigated for the first time. This investigation involves the study of various electrical parameters like drive current (Id-Vgs), threshold voltage (Vth), Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), ION/IOFF, and transconductance generation efficiency...
In this work, the impact of gate material engineering on the performance of RingFET architecture i.e. Dual Material Gate RingFET (DMG-RingFET) has been investigated for the first time using ATLAS 3D device simulation. A fair comparison has also been drawn between the performance of DMG-RingFET and SMG RingFET device architectures. The impact of high-k gate dielectric on the performance of DMG RingFET...
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