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The impact on the reliability of capping layers for low Vt nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is created. While with the cap above the host dielectric the impact...
PBTI and NBTI reliability is investigated on La2O3 and Al2O3 capped n and pMOSFETs, respectively. Low Vth devices are achieved using the capping layers without degrading BTI reliability. For the Al2O3 capped pMOSFETs no additional defects related to the capping are observed. The La2O3 capping layer for nMOSFETs induces shallow traps, which however are not critical at operating conditions.
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