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Laser annealing is an ideal activation step for ultra shallow junctions (USJ). But it can increase the density of interface traps (Dit) of the gate dielectric, resulting in degraded NBTI reliability. Therefore the influence of anneal conditions is studied with corona charge metrology. SiO2 is used as a reference gate dielectric for which recovery solutions are worked out to reduce the laser induced...
In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the...
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