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This paper demonstrates for the first time a low cost, low complexity process CMOS Hk/MG for low-power applications with Vth controlled by gate Ion-Implantation (I/I) and High-k capping for NMOS and PMOS, respectively. Novel advanced electrical and physical characterizations provide unique insights about the underlying mechanism of Vth adjust induced by I/I into the metal. Improved RO performance,...
In this paper, we have done a comprehensive study of the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF. It has been shown that a low long channel Vth is easily achievable with anneal sequence optimization. In particular with the help of laser which creates more dipoles for NMOS case with La-based capping. But also...
The impact on the reliability of capping layers for low Vt nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is created. While with the cap above the host dielectric the impact...
The transistor VT tuning mechanism in metal-gate/high-k (MG/HK) gate stack doped with rare-earth elements (Dysprosium or Dy in this work) is studied in transistors fabricated by either a gate-first or a gate-last approach. Except the commonly believed interface dipole, this work provides additional evidence that the bulk trapping charges can also play an important role in determining the device VT...
We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La2O3, Dy2O3 and Al2O3 on both HfSiO(N) and SiO2 to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have...
In this letter, we report that the application of a thin HfSiON cap layer (2-10 cycles via atomic layer deposition) on SiON host dielectrics in phase-controlled Ni-fully-silicide (FUSI) CMOS technology is effective to modulate the device Vt and reduce the gate leakage while maintaining a similar gate capacitance equivalent thickness and a long channel device mobility (at an Eeff of 0.8 MV/cm). High-V...
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