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This paper describes a static machine code analyzer which helps to eliminate the redundant bank switching instructions in partitioned memory architectures. Our approach rests on a state transition diagram representing the memory bank switching corresponding to each bank selection instruction. Redundant data memory bank selection instructions in the intraprocedural sequence, loops and interprocedural...
A code validation tool for RISC microcontrollers, at the level of machine instruction stream is described. This purports to a methodological approach to achieve software debugging and code validation, where the source code might be created in assembly language or a high level language. The appropriateness of instructions as well as its sequence in a program is validated with the help of rules governing...
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