The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An interconnection scheme for chip-to-chip optical link has been proposed in this work where the silicon substrate of the driver integrated circuit (IC) is used as a subcarrier and also as a light path. This interconnection scheme uses a low loss high speed reconfigurable optical printed circuit board (REOPCB) for coupling light from one chip to the other. A multichip transmitter module has been fabricated...
An electrical/optical (E/O) module integrated with a combined transmitter/receiver (Tx/Rx) and multiplexer/demultiplexer (Mux/Demux) is proposed. With this topology, a high efficient bidirectional optical link can be implemented in the term of saving power consumption, chip area, board area as common blocks are shared between Tx and Rx as well as Mux and Demux. Based on this topology, a design of...
A bidirectional transceiver (Bi-TRx) integrated with a novel transmission envelope detector, which can detect the presence of received signals to generate a mode control signal automatically, is proposed in this letter. Implemented in a 0.18-mum complementary metal-oxide-semiconductor technology, the Bi-TRx occupies an area of 1.08 mm2 , and dissipates 42 and 49 mW in transmitter (Tx) and receiver...
A novel all-digital phase-locked loop (ADPLL) is proposed and designed for chip-to-chip optical interconnect applications. The ADPLL is designed using the TSMC 0.18 mum CMOS technology. The core size of the ADPLL is 550times1040 mum2. The frequency range of the ADPLL is 3.0 - 3.4 GHz and power consumption is 18.67 mA with 1.8 V supply voltage.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.