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A novel all-digital phase-locked loop (ADPLL) is proposed and designed for chip-to-chip optical interconnect applications. The ADPLL is designed using the TSMC 0.18 mum CMOS technology. The core size of the ADPLL is 550times1040 mum2. The frequency range of the ADPLL is 3.0 - 3.4 GHz and power consumption is 18.67 mA with 1.8 V supply voltage.
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