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In this paper, we propose an FPGA memory hierarchy based on the OpenCL memory model. The memory hierarchy allows application-specific memory optimizations during design compilation using information provided in OpenCL kernels. With the proposed memory hierarchy, FPGA application developers can focus on their designs in OpenCL kernel codes, and their designs can be synthesized into FPGA hardware via...
Current studies about decoding Fast protocol in the FPGA platform are always implemented using serial communication technique and for some certain Fast Templates. This paper presents the FPGA hardware design of accelerating the decoding process in parallel and cutting down the cost of changing Fast Templates with flexible decoders. The complete system has been simulated and tested in SystemC Platform.
This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2N - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power...
Network on chip (NoC) implements routers and links onto a single chip. NoC is scalable compared to bus for many-core system. When communication moves from bus to NoC, the single centric memory becomes congested node of network and bottleneck of performance. In this paper, we apply distributed shared memory architecture to a NoC-based multi-processor system. On this hardware platform, we ran a multi-thread...
Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives...
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