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A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples...
This paper reports the first experimental demonstration of improved 1/f noise characteristics in a locally strained Si MOS through hydrogen-controlled stress liners and embedded SiGe (eSiGe). For NMOS, the high hydrogen density (1times1022cm-3) in the stress liner results in three times more noise than that of PMOS. For PMOS, eSiGe proves to be superior to a compressive stress liner in noise due to...
This paper describes a 12-bit, 200-MSample/s current-steering CMOS D/A converter for wireless-communication terminals. To reduce the effects of voltage drops (IR drops) along power supplies, 3-dimensional wiring is applied. The converter was implemented in a 90-nm CMOS technology, and it operates at a low supply voltage of 1.2 V. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free...
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