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This paper discusses critical aspects for co-design of ultra wideband (UWB) system-on-chip (SoC) and on-chip electrostatic discharge (ESD) protection, which are beyond simple data rate and bandwidth considerations. UWB-ESD co-design techniques and experiment results are presented. The designs were implemented in a commercial 0.18 μm RFCMOS.
A 3.1-4.8GHz LNA for lower-band UWB transceiver front-end ICs designed in a commercial 0.18μm CMOS is presented. The LNA features current reuse, resistive feedback, complete and robust full-chip ESD protection. LNA circuits with and without ESD protection are compared to minimize ESD-induced LNA performance degradation. Experiment shows a gain of 13.2dB, excellent input reflection of -13.4dB, NF of...
This paper reports design of a novel low-parasitic ultra-low-triggering voltage dual-directional LTdSCR ESD protection structure in foundry CMOS. It features programmable low triggering voltage of 4.7~6V, low discharging resistance of ~0.77Ω, low leakage of ~0.1nA, extremely low parasitic capacitance of ~10fF and ultra fast response of ~100ps. it achieves ESD protection of >7.8kV HBM and ~500V...
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