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This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source. The post-simulation result indicates that the VCDL has moderate linearity range, low Processing-Voltage-Temperature (PVT) sensitivity and good noise resistance. It can be perfectly applied in the 5Gbps Over-sampling based...
With the wide application of spatial information grid, how to solve the data synchronization has become a current research focus in spatial information grid. Because of the confidentiality and specificity of spatial data, it needs each grid node can only have their own data. When one grid node wants to use the data in another one, it must obey the principle of using the data without owning the data...
In spatial information sharing platform, an important use of the metadata is data searching. Traditional information sharing platform mostly search data just in the central node, which is inefficient. This paper presents a method which improves the efficiency of searching by mobilizing all the nodes of information sharing platform. That is, updating metadata of all the nodes through the synchronizing...
A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle...
The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems. However, the clock skew constrains the improvement of clock frequencies and affects the reliability of systems. One skew reduction technique is the use of clock deskew circuits. They can be classified into two methods: delay-locked loop (DLL) deskewing and synchronous mirror delay...
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