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This paper describes a low power high accuracy K-band quadrature voltage controlled oscillator (QVCO) in 90 nm CMOS process. The gate-modulated coupling and the transformer-feedback technique are employed in the QVCO design to enhance performance. With a dc power consumption of 16 mW, the measured tuning range is from 23.4 to 25.1 GHz, and the output power is higher than −5 dBm. The measured phase...
A 2.2–2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz,...
A W-band divide-by-1.5 injection-locked frequency divider (ILFD) using 90 nm CMOS process is presented in this paper. Due to the fractional frequency division, the proposed divide-by-1.5 ILFD can be employed in a millimeter-wave local oscillation chain to avoid the injection pulling caused by the power amplifier. The measured input locking range is from 91 to 93.7 GHz, and the free-running oscillation...
In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the...
A monolithic DC-70-GHz distributed amplifier (DA) using a 90-nm CMOS process is presented in this paper. The DA is composed of a cascaded single-stage distributed amplifier (CSSDA) and a conventional distributed amplifier (CDA). The CSSDA is adopted as the first-stage to increase the small-signal gain of the DA. The CDA is adopted as the second-stage for the higher output power. Moreover, the modified...
A monolithic DC-70-GHz distributed amplifier (DA) using a 90-nm CMOS process is presented in this paper. The DA is composed of a cascaded single-stage distributed amplifier (CSSDA) and a conventional distributed amplifier (CDA). The CSSDA is adopted as the first-stage to increase the small-signal gain of the DA. The CDA is adopted as the second-stage for the higher output power. Moreover, the modified...
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