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For the first time, we present good yielding 64 Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28 nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32 nm node with gate density of 2.3times higher than that of 45 nm, and integrates high density (0.127 um2) and low Vccmin (0.155 um2) 6-T SRAM cells, low power...
For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at...
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