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System-on-a-chip (SOC) uses embedded cores those require a test architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach may also be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). This paper presents an algorithm for minimizing the post bond test time for 3D core-based SOCs under the...
Design of core based three dimensional (3D) system-on-chip (SOC) is gaining a remarkable attention in modern days' semiconductor industry. Testing of 3D SOC is considered as one of the important challenge and hence efficient test techniques are required. The objective of this paper is to design efficient test access mechanism (TAM) and test scheduling architecture of different cores of the SOC such...
In this work, we present an efficient reversible implementation of Carry-Lookahead Adder (CLA) in all-optical domain. Now-a-days, semiconductor optical amplifier (SOA)-based Mach -- Zehnder interferometer (MZI) plays a vital role in the field of ultra-fast all-optical signal processing. We have used all optical based Mach-Zehnder Interferometer (MZI) switches to design the CLA circuit implementing...
In recent years Digital Micro-fluidic Bio-chips have become a suitable choice for point of care diagnostics. These devices can detect various properties of human blood by means of an optical detection technique. The data acquisition is generally done using a LED-photodiode setup working in conjunction with the biochip. The voltage signal obtained at the photodiode output needs to be converted into...
In this work, we present all optical reversible implementation of Flip-Flops using semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. Improved design of MZI-based functionally reversible RS, D, JK, T and three different implementations of all optical functionally reversible MZI-based Master-Slave Flip-Flop using RS, D and JK Flip-Flop are presented. Detailed analysis...
In this work, we propose an architecture for optical detection based analyzer to be integrated with Digital Microfluidic Biochips (DMFB). A reference memory has been integrated with the device to define pre-characterized data for the multiple reference levels. The architecture has been developed towards the implementation of the fuzzy based control of the process flow for extending the analysis to...
Digital Microfluidic Biochips (DMFB), a promising platform for Lab-on-chip systems are capable of automated biochemical analysis targeted for medical diagnostics and other biochemical applications. The inherent nature of reconfigurability and scalability enables the device to integrate multiple bioassay protocols within the same array for simultaneous execution. Each execution of Bioassay involves...
Crosstalk effects in Multilayer Graphene Nano Ribbon interconnects (GNRs) are investigated with the help of ABCD parameter matrix approach for intermediate and global level interconnects at 11 nm technology node. For long intermediate and global levels of interconnects, the worst case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are far lesser than that of copper interconnects...
This work proposes an ESOP-based technique for the synthesis of reversible circuit using a paired cube approach. In this method, initially we provide an ESOP as input and generate an optimized cube structure. Next, the pairing of ESOP cubes based on their structural similarity is performed to design improved reversible circuit using Toffoli gates. Experimental result shows that the paired cube synthesis...
Digital microfluidic biochips in recent years have been developed as a major alternative platform for conventional benchtop laboratory procedures. It offers better precision, scalability, higher sensitivity, lower cost due to smaller sample and reagent volumes. Testing of DMFBs is of major significance in terms of dependability and reliability issues for safety-critical applications. A series of complex...
Synthesis of reversible circuits has attracted the attention of many researchers. In particular, approaches based on Decision Diagrams (DDs) have been shown beneficial since they enable the realization of corresponding circuits for large functions. However, all existing approaches rely on a gate library composed of positive control lines only. Recently, it has been shown that the additional use of...
Charge-pump adds/removes charges to/from a loop-filter via constant current source/sink. Channel length modulation effect in the locking range of DLL (Delay Locked Loop) worsens the matching between this current source and sink. A new feedback circuit based charge-pump is proposed here to reduce this mismatch for PET (Positron Emission Tomography) imaging applications. Simulations are performed in...
The work in this paper, presents the analysis of electrical transport in graphene nanoribbon (GNR) interconnect as next generation on-chip interconnect. Graphene has the potential of performing as an interconnect material that could replace the existing copper interconnects in future silicon based micro chip. In this work, we have investigated how the mean free path (MFP) of electron in graphene can...
Three dimensional (3D) VLSI integration based on through-Silicon-Via (TSV) is an emerging technology. It provides heterogeneous integration, higher performance, bandwidth, and lower power consumption. However, 3D-IC suffers from several challenges. The objective of this paper is to design the test access mechanism (TAM) architecture and test scheduling of different modules of an system-on-chip (SOC)...
Due to continued scaling of feature sizes, signal integrity and performance of today's copper based nanoscale interconnects are severely impacted. In this work, an ABCD parameter based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper based nano-interconnect systems. Using the proposed analytical model, the crosstalk delay and noise are...
There are diverse hardware realization for digital watermarking of multimedia proposed in the literature. This paper focuses on the design and implementation of a fast FPGA(Field Programmable Gate Array) based architecture using reversible contrast mapping (RCM) based image watermarking algorithm. The specialty of this architecture attracts to the fact of clock-less encoder design and implementation...
The work in this paper presents analysis of graphene nanoribbon (GNR) as nano-interconnect for radio-frequency (RF) VLSI circuits for 16 nm technology node. A frequency dependent electrical equivalent model is developed by calculating the circuit parameters based on interconnect geometry. Using the developed model the RF performance of GNR based interconnects is investigated and compared to that of...
The development of efficient techniques for reversible quantum circuit synthesis has received significant attention now-a-days due to recent emphasis on low power circuit design. This work presents two new deterministic methods, which evaluate the NPRM structure of logic functions. After extracting the structure, the synthesis of ESOP based reversible logic is performed using NPRM form. The first...
In a wireless sensor network (WSN), random occurrences of faulty nodes degrade the quality of service of the network. In this paper, we propose an efficient fault detection and routing (EFDR) scheme to manage a large size WSN. The faulty nodes are detected by neighbour node’s temporal and spatial correlation of sensing information and heart beat message passed by the cluster head. In EFDR scheme,...
This paper presents a compact, semiconducting behavior zigzag model of carbon nanotube field effect transistor. The model is based on analytical approximations. We have done the performance analysis of the developed model and the comparisons of the performance parameter like surface potential, drain current, quantum capacitance, average velocity against chirality of zigzag CNTFET model using numerical...
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