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This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set...
Hybrid pixel detectors are becoming a standard in modern fast X-ray imaging for material science, physics and medicine. However, charge sharing effect is the main limitation in increasing position resolution of these systems and also for using them for spectroscopy applications. In this paper we present novel algorithms which allow proper hit allocation even in the case of charge sharing and which...
This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power...
We have designed, fabricated in 90 nm technology and tested a prototype ASIC for readout of semiconductor pixel detectors for X-ray imaging applications. The 4mm x 4mm readout IC is working in single photon counting mode and contains a pixel matrix of 1280 readout channels with dimensions of 100 µm × 100 µm each. We present the architecture, the measurement results of this IC and our conclusions....
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