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In this paper, we investigate register multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write...
Interconnection networks for multicore processors are designed in a generic way to serve a diversity of workloads. For multicore processors, there is a considerable opportunity to achieve an improvement in performance by implementing interconnects which adapt to different program phases and to a variety of workloads. This paper proposes one such interconnection network for medium-scale (up to 32 cores)...
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