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The calculation of the threshold crossing time of the on-chip very large scale integration (VLSI) interconnects is an important part of interconnect simulation. The paper focuses on low-loss on-chip upper layer interconnect simulation. The work presents a new way of calculating the closed form output voltage and threshold crossing time formulas based on differential equation multiple scales solving...
In the paper we present the approach in order to estimate a crossing time of the step response for the lossless and low-loss transmission lines. There is derived a closed form solutions to the crossing time for such lines when the overshoots appear. For the low-loss lines the method bases on the simplification that allows to specify the exact terms in the step response calculations
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