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The redundant via (RV) insertion is a widely used technique to enhance chip reliability. However, inserting an RV adjacent to a single via (SV) may create extra critical area (CA) between nets and worsen the circuit’s yield. In this paper, we present a short CA (SCA)-constrained RV insertion method for yield optimization with a consideration of the SCA. First, we find the candidate ranges of the SVs,...
The safe-operating-area (SOA) of automotive DMOS transistors, which are operated repeatedly under high power pulses (power cycling), is lower than the classical single-pulse SOA and it is dependent on the geometry of the transistor. In this paper, we present a test system for reliability characterization of power devices, of various geometries, which operate under power cycling conditions.
This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate...
Environmental regulations around the world have been targeted to eliminate the usage of leaded solders in electronic assemblies. Sn-Zn based alloys are considered to be a very promising candidate for its substantially same melting point as Sn-Pb solder. Fujitsu Limited has developed several lead-free solders with low melting point such as Sn-7Zn-30 ppmAl and Sn-9Zn-30ppmAl. Those solders have already...
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