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The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells. It allows hardware amount decrease without...
A method of combined state assignment is proposed which targets on a decrease in the hardware amount (the number of PAL macrocells) in combinational part of Moore finite-state-machine (FSM). Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount. It...
The method for decrease of the number of PAL macrocells in the circuit of Moore FSM is proposed. This method is based on the implementation of free outputs of embedded memory blocks to represent the code of the class of pseudo equivalent states. The proposed approach allows minimize the hardware without decreasing digital system performance. An example of application of the proposed method is given.
Method of decrease of number of PAL macrocells in circuit of Moore FSM is proposed. Method is based on use of free outputs of embedded memory blocks to represent a code of a class of the pseudoequivalent states. Proposed approach permits to decrease the hardware amount without decrease of a digital system performance. An example of application of proposed method is given.
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