The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents performance evaluation of high-kappa/metal gate (HK/MG) process on an industry standard 45 nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45 nm Poly/SiON devices. No additional stress elements were used for this performance gain...
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress...
This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which...
Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (Lg= 2 mum), 10% higher at short channel (Lg = 36 nm) compared to (110) bulk PFETs. Moreover,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.