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Parameters of interconnection lines have an effect on the electrical parameters of modern VLSI chips, so precise models of interconnection capacitances are indispensable in verification of the design. In our previous works we have shown importance of geometric configuration of the interconnection bus, taking into account further neighbourhood, and proposed a model of corresponding capacitances, verified...
In our previous works we have proposed an empirical model of interconnection capacitances, taking into accountfurther neighborhood of the line in the bus. The model was developed for technologies based on SiO₂ as the isolating material between interconnection lines and metal layers, and it was verified numerically and experimentally [1,2]. In most advanced technologies Iow-k materials displace SiO₂,...
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