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Noise generated by digital sub-circuits becomes a serious problem in fast mixed signal system on chips (SoCs). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. The circuits for substrate noise suppression proposed so far have serious weaknesses due to their frequency limitations. We present a method for optimization of noise-suppressive...
This paper presents an efficient method for supply-current spectrum estimation for the static CMOS family of digital gates. It extends the previous approach (Blackiewicz, 2006), that considered only the noise due to a gate output switching, by including the noise generated by glitching, and short impulses. Estimation of digital circuit noise is used in early design planning of modern mixed-signal...
We consider a test-scheduling problem, with layout constraints, for core-based SOCs. Individual cores have to be tested on a system level after manufacturing and therefore special test access mechanisms (TAMs) are required. The amount of additional wires needed to route TAMs depends strongly on a SOC layout. In this research, we investigate the SOC test-scheduling problem formulated as the bin-packing...
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