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Summary. Antiviral therapy is a potentially successful approach for the treatment of patients with Hepatitis B virus (HBV) infection. One antiviral agent is the nucleoside analogue adefovir dipivoxil (ADV). Its efficiency is compromised by the emergence of drug‐resistant HBV mutants. Although three major ADV‐resistant mutations of HBV are known, rtA181T/V and rtN236T, HBV mutations associated with...
In this work, a directed assembly technique for controlled micro-patterning of single-walled carbon nanotubes (SWNTs) on to a flexible parylene-C substrate has been demonstrated. A simple site-selective fluidic assembly of SWNTs has been utilized to directly assemble SWNTs on a plasma treated parylene-C substrate to form ordered high density carbon nanotube networks. Continuous nanotube micro-arrays...
In this paper, we demonstrate the integration of single-stranded-DNA (ss-DNA) decorated single-walled carbon nanotubes (SWNT) onto complementary metal oxide semiconductor (CMOS) circuitry for gas sensing applications. Utilizing dielectrophoresis (DEP) assembly, a simple and a low temperature process, we first demonstrate integration of SWNTs onto CMOS circuitry at the die level. SWNTs are sensitive...
Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed...
Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
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