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In this paper we show that devices in scaled technologies could undergo self-heating (SH) even in the off-state when subjected to stress conditions that would in turn adversely impact product life-time. We present a detailed methodology in analyzing the impact of off-state SH, thus preventing unintentional overstressing during product stress-screening. We propose an analytical model for modeling this...
We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 µA/µm at Ioff = 10 nA/µm at VDD = 0.8 V. The BOTS process results...
We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6 nm-diameter). The technology is also extended to an independent double gate memory architecture, called Φ-Flash. The experimental results with 6 nm nanowires show high programming windows (up to 7.4 V), making the structure compatible with multilevel operation...
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