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In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results...
This paper discuss the use of the FPGA as a controller of a DC-DC boost converter, the goal of this paper is to build a controller that is capable of controlling the output current of a photovoltaic cells and minimize the effect of the boost converter chaotic behavior on the output voltage. The paper also presents a MATLAB simulation of the system to evaluate and study the effect of the duty cycle...
The last decade has a rapid development in the structure of a programmable processor called Field Programmable Gate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed application. Sobel edge detection is a method to find the edge pixels in an image. This method exploits the change in intensity with respect to neighboring pixels. This paper introduces...
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC)...
This paper proposes a fifteen level H-Bridge cascaded multilevel inverter with fundamental frequency switching for low power applications such as solar powered power supplies, battery powered standby power supplies. The effect of the variation of gate pulse on the performance of the inverter for different conditions of gate pulse variation is studied and simulation results are presented. Experimental...
Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT's for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable...
This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions...
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