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The reduction of detectors in PET systems, without significantly compromising the PET utility, is an important cost consideration in a PET-system design. Recent advances in algorithm development can be used for enabling the design and assessment of innovative PET systems. In this work, we investigate PET configurations with reduced number of detectors by using the ASD-POCS algorithm that was developed...
A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >100µs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process...
Multi-threshold CMOS is a very effective technique for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme suffers from high sensitivity to process variations, which impedes manufacturability and also limits its applicability...
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at Ioff = 100 nA/µm for high performance (HP) and 920/880 µA/µm at Ioff = 1 nA/µm for low power (LP), respectively, at VDD = 1 V. High...
We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 µm2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node [1]. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50...
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