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We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10×12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 μm2 per cell, and is...
We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The...
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