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Today, both the rapid improvement of process technology and the arrival of new embedded systems with highperformance requirements, have led to making the current trend in processors manufacturing shift from single-core processors to multi-core processors. This trend has raised several challenges for reliability in safety-critical systems that operate in high-risk environments, making them more vulnerable...
This paper describes a design approach for incorporating sequence-aware watermarks in soft intellectual property (IP) embedded processors. The influence of watermark sequence parameters on detection, area, and power overheads is examined, and consequently a method for incorporating sequence-aware watermarks in soft IP embedded processors is proposed. The intrinsic parameters of sequences, such as...
This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication...
In this paper we presents the design of a very low power and high throughput AES processor. A sophisticated AES algorithm without sacrificing its security features, throughput and area is used to design the processor. Due to the optimization of the algorithm and a number of design considerations, the processor shows its superiority over other AES processors. The proposed processor is simulated on...
Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation...
Security is a prime concern in the design of a wide variety of embedded systems and security processors. So the customer security devices such as smart cards and security processors are prone to attack and there are on going research to protect these devices from attackers who intend to extract key information from these devices. Also an active attacker can induce errors during computation and exploit...
The elliptic curve cryptography can be observed as two levels of computations, upper scalar multiplication level and lower point operations level. We combine the inherited parallelism in both levels to reduce the delay and improve security against the simple power attack. The best security and speed performance is achieved when parallelizing the computation to eight parallel multiplication operations...
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