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In this paper, we developed 60V rated fully isolated LDNMOS which can be available under negative bias condition. Double epi process for obtaining higher BVdss, PBL (p+ buried layer) for retarding punch through and NBL-2 (n+ buried layer) for a role of electrically connecting NBL-1 are adopted to achieve 60V rated fully isolated LDNMOS. This optimized device has characteristics of Ron.sp 55mohm*mm...
A BJT named ‘biristor’, a term derived from ‘bi-stable resistor’, is demonstrated for 4F2 high speed volatile memory applications. For a floating body cell, a gate-less vertical silicon pillar, which is an n-p-n BJT with an open-base, is employed, whereas for its control device, a MOSFET composed of a vertical silicon pillar surrounded by a gate is utilized. A 4F2 memory cell array is realized by...
In this paper, we present a new isolated Low Vgs NLDMOS in 0.35um BCDMOS process. The proposed LDMOS is fully isolated from substrate and has very lower Rsp(specific on-resistance) than other competitors. This device can apply a negative bias to drain and it can be used in AMOLED application. The proposed LDMOS devices in 30–40V ranges have the lowest Rsp with other competitors in 0.13–0.35um BCDMOS...
Growth, fabrication, and characterization for a type II lineup InAs/AlSb HFET are presented. An as-grown epitaxy wafer with a 300 K mobility of 21,300 cm2/V-s and an electron sheet concentration of 1.4times1012 cm-2 was processed into devices. Peak transconductance of 720 mS/mm and drain current of 650 mA/mm at drain voltage of 1.0 V are achieved in a 1-mum gate length device. It is observed strong...
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