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With relentless scaling of transistor dimensions, the single cell soft error rate (SER) reduces with each technology node [1]. InGaAs and Ge complementary FinFET technology is promising for next generation NMOS/PMOS FETs, due to their superior transport properties [2] over silicon, but their soft error performance is unexplored to date. Previous work investigated the SER in InAs nFinFET assuming symmetrical...
Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary ‘all III–V’ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |VDS|=0.5V. The p-type TFET (PTFET) has ION =30µA/µm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275µA/µm and ION/IOFF=3×105, respectively...
The ∼20% Id,sat improvement is demonstrated successfully on the Si and Ge n-FinFETs with the implement of D-SMT stressor for the first time, based on the optimization of dislocation angle and the understanding of crystal re-growth velocities along different surface planes and directions in Si and Ge. The mobility enhancement ratio with D-SMT stressor in Ge n-FinFET (37%) is found to be larger than...
Tunnel transistor (TFET) is a potential steep slope device enabling supply voltage scaling. TFET is explored at the device and circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry can outperform Si FinFET at Vcc<;0.3V. Design considerations of TFET based circuits for logic and SRAM applications...
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