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With the use of non-tree topology in signal nets, the delay issue in non-tree topologies has become an important problem. In this paper, based on the transformation-based timing analysis for a non-tree interconnection, an iterative wire-sizing approach is proposed to assign feasible widths onto the wire segments to minimize the timing delay in the critical path for a non-tree interconnection under...
Based on the assumption of a single wiring open in a signal net, it is known that the non-tree topology for a signal net has no adjacent loop. In this paper, based on RC non-tree transformation in Elmore delay model, an optimal algorithm for timing analysis is firstly proposed to compute the timing delays of all the reference nodes in a non-tree topology. Compared with the SPICE tool, the experimental...
Designs with non-tree consideration have been proven to improve the yield and reliability in modern chips. In this paper, an efficient three-phase approach for transformation-based timing analysis is proposed to transform a cyclic graph into an acyclic graph by using the node-splitting operation and compute the delay of the transformed tree-based circuit in an Elmore delay model. Compared with the...
In this paper, given a set of connecting nodes in a signal net, based on the result of optimal wire width and buffer insertion in a wire segment (Yan, 2006) and the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective tree construction approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing, buffer insertion and obstacle avoidance...
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