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A binary neural associative memory concept comprising nanoelectronic resistive switches and non-linear selector devices used as binary connection elements is proposed for the realization of logic and arithmetic functions. Based on the consideration of device variability an error detecting 2-out-of-n-code for the representation of operands is developed. The connection structure of an associative memory...
The key challenge of wireless sensor nodes is their total power dissipation, hampering their autonomous operation due to limited battery life time. Aggressive voltage scaling reduces both dynamic and leakage power, prolonging the battery life time. The challenges of aggressive voltage scaling into the subthreshold region includes the pronounced effect of process variability and the significantly reduced...
Today, high-performance divider implementations almost always use the classical SRT algorithm in conjunction with a redundant residual representation like carry-save. In this paper, a modified approach is presented, which reduces the number of comparisons inside the quotient digit selection function (QDSF) to the number necessary in a non-redundant implementation of the same radix. To keep the overlap...
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