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A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier...
This paper presents the design and the performance of a low-noise front-end readout application specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager. A cascode amplifier based on split-let topology is proposed to realize the charge-sensitive amplifier (CSA) for the sake of a single positive power supply. A leakage-current-compensation circuit is added to suppress the...
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