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In this paper, a robust, low-complexity timing synchronization algorithm suitable for 5.9 GHz advanced dedicated short range communications (ADSRC) system and its efficient hardware implementation is proposed. Cross-correlation technique is used to detect the starting point of short training symbol and the guard interval of the long training symbol. The design is implemented in a Xilinx Vertex-II...
In this paper, a robust, low-complexity timing synchronization algorithm suitable for 5.9 GHz dedicated short range communications (DSRC) system is proposed. The proposed method uses cross-correlation technique to detect the starting point of both a short training symbol and the guard interval of the first long training symbol. This allows the proposed algorithm to have low-complex architecture. Compared...
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